1. Field of the Invention
This invention relates to the field of integrated circuit (IC) interconnections, and particularly to wired and wireless systems and methods of effecting inter- and intra-chip interconnections.
2. Description of the Related Art
Chip-to-chip communications—i.e., the transfer of data between different ICs within a system—are under ever-increasing pressure to perform faster. This is particularly true for bus-based communications between a CPU and RAM in a computer system.
The traditional chip-to-chip communication speed on a printed circuit board (PCB) is usually much lower than the speed of a CPU. Thus, chip-to-chip communication speed usually limits system performance. In particular, the bandwidth and latency of memory systems have been limiting factors for system performance. This so-called “memory wall” has been the subject of much research, and there have been numerous dynamic RAM (DRAM)-oriented approaches to increase DRAM bandwidth or reduce DRAM core access latency. In the current PC industry, 1.1 GB/s PC133 SDRAM, 1.6 GB/s Direct-Rambus DRAM (D-RDRAM) and 2.1 GB/s DDR266 are the most popular products focusing on DRAM bandwidth. However, the approaches taken by these RAM systems—which each rely on a traditional memory bus interface—can only do so much, as they are designed for system architectures having many sources of overhead. For instance, even with a DRAM core access latency of zero, the overhead of any of these memory systems would not reduce to zero, because bus transactions still require time on the channel.
The costs associated with DRAM memories increases with the number of I/O pins on the DRAM package. The performance of a memory system could be increased somewhat by widening memory channels and by providing independent DRAM banks. However, both these approaches increase cost; furthermore, channel latency and concurrency problems still exist. FIGS. 1(a) and 1(b) show two typical primary memory bus configurations, in which n DRAM chips 10 are connected to a common data bus 12 and to an address/control bus 14, and the bus lines are connected to a CPU 16 and a memory controller 18 interconnected as shown. If these configurations utilize a conventional memory bus, such as the high-speed narrow channels used in D-RDRAM, they suffer from long channel latency: for instance, if two read requests arrive at DRAM1 back-to-back or two read requests arrive at DRAM1 and DRAM2, respectively, the second request must stall until the first request finishes using the shared data bus. Increasing bus speed improves performance, but channel request latency still exists.
To send or receive 1 bit of data on a conventional bus interface using a data channel, one physical PCB line and two transceivers are needed. As illustrated in FIG. 2, sending or receiving 2 bits of data at the same time requires 2 PCB lines 20, 22 and 4 transceivers 24, 26, 28, 30 (which connect to DRAM chips 32, 33 via respective interface circuits 34, 35); the transceivers are typically connected to the PCB lines via I/O pads 36. Increasing data bandwidth requires an increase in bus frequency and/or the number of parallel PCB lines. But, high frequency parallel lines create crosstalk noise and degrade signal integrity. To mitigate this, the number of data and address lines should be equal, and extra shielding lines should be used on the PCB. However, this causes the die size and package size to increase, and thus complicates PCB design.
Other memory bus systems have attempted to solve the problems of high-speed access to memory with limited success. For example, in U.S. Pat. No. 3,969,706 to Proebsting et. al., a DRAM interface is described. The address is two-way multiplexed, and there are separate pins for the data and control lines (RAS, CAS, WE, CS). However, under this approach, the number of I/O pins must increase with the size of the DRAM, with the pin count possibly becoming unacceptably large with the high capacities of modern-day DRAM chips.
U.S. Pat. No. 6,128,696 to Farmwald et. al. describes a D-RDRAM system, which receives address and control information over a data bus in packet form and transmits or receives request data over the same bus. This “Rambus” system is divided into three sections: a DRAM core, a memory interface, and an I/O interface. The I/O interface section is connected to the communication channels with a plurality of pins. By running the bus at a 400 MHz clock rate and using 16 data channels and 8 address channels, a peak bandwidth of 1.6 Gbyte/s can be achieved.
However, though D-RDRAMs can reduce the number of I/O pins needed by using a high speed bus interface, they typically require a number of shielding pins to reduce the cross-talk noise and inter-symbol interference (ISI) effects on the PCB board. The result is a negligible reduction in the total number of data, address, supply, and ground pins needed. D-RDRAMs may also require a 184 pin package, which increases chip cost.
Device properties also have a significant effect of chip-to-chip communications. To enhance circuit and system performance, considerable effort has been expended on improving device speed by reducing the device dimensions. This decrease in minimum feature size has led to a proportional decrease in the cross-sectional area and pitch of metal interconnects (“wires”). As a result, the parasitic resistance, capacitance and inductance associated with an IC's wires are beginning to adversely affect circuit performance, and have increasingly become a primary stumbling block in the evolution of deep sub-micron ultra-LSI (ULSI) technology. Recent studies have indicated that when feature sizes fall below 1 μm, the interconnect parasitics cause signal attenuation and dispersion in the wires, seriously hurting circuit and system performance. These problems become even more acute when the bit rate capacity exceeds ˜1016 A/l2, where A is the cross sectional area of the interconnect wiring and l is the length of the wire. The RC (or LC) time delay, IR voltage drop, CV2f power loss and crosstalk parameters of an IC's wires also become significant at higher bit rates.
For the past few years, a great deal of work has been focused on improving conventional interconnect technology by reducing the resistivity of conductors (using copper, for example) and reducing the dielectric constant of interlayer dielectric materials (by using low-κ polymers, for example). Nevertheless, these evolutionary approaches may soon encounter fundamental material limits which will inhibit further feature size reductions and/or bit rate increases.